Memory Consistency is talking about how to deal with problems like store and load data in different addresses in multi-core or multi-thread system.
key point is the OoO would reorder the instruction execute order.
after reordering we can't promise lw could get the correct data.
MYSYNC is a choice to solve this , this ins could make sure ins after this would not be reordered. e.g. ll and sc
lw var and ll sc, sw var and sw 0,lock have different target address, so they probably would be reordered, like lw var exe before ll/sc. Therefore we add MYSYNC to prevent it.
two other choices are relaxed and fixed. relaxed means we specify one or more type of (Write or Read A->Read or Write B 2*2 4 types) which can't be reordered (program should know this and give code according to it). fixed: program order: l A ---> lB .execution order: LB---->LA(a snoop is here, if it notice a SB, then erase LB data and redo it)
MODELS of consistency
1. sequential model
2. relaxed model (key point is to tell the prgram wihich part can or can't be reodered)
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Sequential consistency ensures that all memory accesses execute as if we process them one at a time, each time selecting a core and letting it complete its next access in program order. Note that this does not require round-robin selection of cores – it even allows one core to be selected several times in a row. This allows for many possible interleavings of accesses from different cores, but it prevents accesses from one core from being reordered.
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Weak consistency distinguishes between synchronization and non-synchronization accesses. Synchronization accesses (such as those used to acquire or release a lock) are never reordered amongst themselves or with other accesses. This means that synchronization accesses are done in a sequentially-consistent way, but non-synchronization accesses that a core makes between synchronization accesses can be reordered freely (note that this reordering is still limited by coherence and dependences in program order).
